LTC3127 [Linear Systems]
40V, 2A Synchronous Buck-Boost DC/DC Converter; 40V ， 2A同步降压 - 升压型DC / DC转换器
| 型号： | LTC3127 |
| 厂家： | 
Linear Systems |
| 描述： | 40V, 2A Synchronous Buck-Boost DC/DC Converter |
| 文件： | 总40页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3115-1
40V, 2A Synchronous
Buck-Boost DC/DC
Converter
FEATURES
DESCRIPTION
TheLTC®3115-1isahighvoltagemonolithicsynchronous
buck-boostDC/DCconverter.Itswide2.7Vto40Vinputand
output voltage ranges make it well suited to a wide variety
of automotive and industrial applications. A proprietary
low noise switching algorithm optimizes efficiency with
input voltages that are above, below or even equal to the
output voltage and ensures seamless transitions between
operational modes.
n
Wide V Range: 2.7V to 40V
IN
n
Wide V
Range: 2.7V to 40V
OUT
n
n
1A Output Current for V ≥ 3.6V, V
= 5V
IN
OUT
2A Output Current in Step-Down Operation
for V ≥ 6V
IN
n
n
n
n
Programmable Frequency: 100kHz to 2MHz
Synchronizable Up to 2MHz with an External Clock
Up to 95% Efficiency
30µA No-Load Quiescent Current in Burst Mode®
Operation
Programmable frequency PWM mode operation provides
low noise, high efficiency operation and the ability to syn-
chronizeswitchingtoanexternalclock.Switchingfrequen-
ciesupto2MHzaresupportedtoallowuseofsmallvalued
inductors for miniaturization of the application circuit. Pin
selectable Burst Mode operation reduces standby current
and improves light load efficiency which combined with a
3µAshutdowncurrentmaketheLTC3115-1ideallysuitedfor
battery-powered applications. Additional features include
output disconnect in shutdown, short-circuit protection
and internal soft-start. The LTC3115-1 is available in ther-
mally enhanced 16-lead 4mm × 5mm × 0.75mm DFN and
20-lead TSSOP packages.
n
n
n
n
n
n
Ultralow Noise Buck-Boost PWM
Internal Soft-Start
3µA Supply Current in Shutdown
Programmable Input Undervoltage Lockout
Small 4mm × 5mm × 0.75mm DFN Package
Thermally Enhanced 20-Lead TSSOP Package
APPLICATIONS
n
24V/28V Industrial Applications
n
Automotive Power Systems
n
Telecom, Servers and Networking Equipment
FireWire Regulator
Multiple Power Source Supplies
L, LT, LTC, LTM, Burst Mode, LTspice, Linear Technology and the Linear logo are registered
n
trademarks and No R
is a trademark of Linear Technology Corporation. All other
SENSE
trademarks are the property of their respective owners. Protected by U.S. Patents including
6404251, 6166527 and others pending.
n
TYPICAL APPLICATION
Efficiency vs VIN
10µH
95
I
= 0.5A
LOAD
0.1µF
0.1µF
90
85
80
75
70
BST1 SW1
PV
SW2 BST2
PV
5V
I
= 1A
LOAD
2.7V TO
40V
1A V > 3.6V
OUT
IN
IN
2A V ≥ 6V
IN
4.7µF
47µF
V
IN
33pF
15k
1M
LTC3115-1
3300pF
60.4k
BURST PWM
OFF ON
PWM/SYNC
RUN
VC
FB
PV
V
249k
CC
CC
RT
GND
PGND
47.5k
4.7µF
(OPTIONAL)
40
31151 TA01b
3115 TA01a
2
10
INPUT VOLTAGE (V)
31151f
1
LTC3115-1
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V , PV , PV
........................................ –0.3V to 45V
V
V
.....................................V
.....................................V
– 0.3V to V
– 0.3V to V
+ 6V
+ 6V
IN
IN
OUT
BST1
BST2
SW1
SW2
SW1
SW2
V
V
V
SW1
DC........................................... –0.3V to (PV + 0.3V)
Pulsed (<100ns)......................–1.5V to (PV + 1.5V)
SW2
DC.........................................–0.3V to (PV
Pulsed (<100ns).................... –1.5V to (PV
RUN
Voltage, All Other Pins ................................. –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 4)
LTC3115E-1/LTC3115I-1 ..................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
IN
IN
+ 0.3V)
+ 1.5V)
OUT
OUT
............................................. –0.3V to (V + 0.3V)
FE......................................................................300°C
IN
PIN CONFIGURATION
TOP VIEW
PGND
RUN
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
PGND
TOP VIEW
PWM/SYNC
SW1
RUN
SW2
1
2
3
4
5
6
7
8
16 PWM/SYNC
15 SW1
SW2
PV
PV
IN
OUT
PV
OUT
14 PV
IN
GND
GND
VC
BST1
BST2
21
PGND
GND
13 BST1
12 BST2
PGND
17
GND
VC
PV
CC
11 PV
CC
FB
V
IN
FB
10
9
V
IN
V
CC
RT
V
CC
RT
PGND 10
PGND
DHD PACKAGE
FE PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
20-LEAD PLASTIC TSSOP
T
= 125°C, θ = 43°C/W, θ = 4.3°C/W
JMAX
JA JC
T
JMAX
= 125°C, θ = 38°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 21) IS PGND, MUST BE SOLDERED
TO PCB FOR RATED THERMAL PERFORMANCE
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3115EDHD-1#PBF
LTC3115IDHD-1#PBF
LTC3115EFE-1#PBF
LTC3115IFE-1#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3115EDHD-1#TRPBF 31151
LTC3115IDHD-1#TRPBF 31151
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
16-Lead (5mm × 4mm) Plastic DFN
16-Lead (5mm × 4mm) Plastic DFN
20-Lead Plastic TSSOP
LTC3115EFE-1#TRPBF
LTC3115IFE-1#TRPBF
LTC3115FE-1
LTC3115FE-1
20-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
31151f
2
LTC3115-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are for TA = 25°C (Note 2). VIN = 24V, VOUT = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
2.7
2.7
TYP
MAX
40
40
2.7
2.8
2.725
UNITS
l
l
Input Operating Voltage
Output Operating Voltage
Input Undervoltage Lockout Threshold
V
V
V
V
V
l
l
V
IN
V
IN
V
IN
Falling
2.4
2.6
Rising
Rising (0°C to 125°C)
Input Undervoltage Lockout Hysteresis
100
2.4
200
3
50
1000
mV
V
l
V
V
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
V
Falling
2.6
10
CC
CC
mV
µA
µA
kHz
kHz
kHz
V
ms
mV
%
nA
V
V
nA
mV
A
CC
Input Current in Shutdown
Input Quiescent Current in Burst Mode Operation
Oscillator Frequency
Oscillator Operating Frequency
PWM/SYNC Clock Input Frequency
PWM/SYNC Input Logic Threshold
Soft-Start Duration
V
V
= 0V
RUN
= 1.1V (Not Switching)
FB
l
l
l
l
R = 35.7k
900
100
100
0.5
1100
2000
2000
1.5
T
1.0
9
1000
0.1
1
0.8
1.21
500
100
3.0
1.5
1.0
95
l
Feedback Voltage
977
1017
Feedback Voltage Line Regulation
Feedback Pin Input Current
RUN Pin Input Logic Threshold
RUN Pin Comparator Threshold
RUN Pin Hysteresis Current
RUN Pin Hysteresis Voltage
Inductor Current Limit
Reverse Inductor Current Limit
Burst Mode Inductor Current Limit
Maximum Duty Cycle
V
V
= 2.7V to 40V
IN
50
1.1
1.26
l
l
0.3
1.16
Rising
RUN
l
(Note 3)
Current into PV
(Note 3)
Percentage of Period SW2 is Low in Boost Mode,
R = 35.7k (Note 5)
2.4
3.7
(Note 3)
A
A
%
OUT
0.65
90
1.35
l
l
T
Minimum Duty Cycle
Percentage of Period SW1 is High in Buck Mode,
R = 35.7k (Note 5)
0
%
T
SW1, SW2 Minimum Low Time
N-Channel Switch Resistance
R = 35.7k (Note 5)
100
ns
T
Switch A (From PV to SW1)
150
150
150
150
mΩ
mΩ
mΩ
mΩ
IN
Switch B (From SW1 to PGND)
Switch C (From SW2 to PGND)
Switch D (From PV
to SW2)
OUT
N-Channel Switch Leakage
PV = PV
= 40V
OUT
0.1
10
5.5
4.58
µA
V
V
%
%
mA
mV
µA
IN
PV /V External Forcing Voltage
4.58
4.33
CC CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Regulation Voltage
Load Regulation
Line Regulation
Current Limit
Dropout Voltage
Reverse Current
I
I
I
= 1mA
= 1mA to 20mA
= 1mA, V = 5V to 40V
4.45
1.2
0.5
110
50
VCC
VCC
VCC
IN
V
CC
= 2.5V
50
I = 5mA, V = 2.7V
VCC IN
V
CC
= 5V, V = 3.6V
10
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
junction temperature range are ensured by design, characterization and
correlation with statistical process controls. The LTC3115I-1 specifications
are guaranteed over the –40°C to 125°C operating junction temperature
range. The maximum ambient temperature is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 2: The LTC3115-1 is tested under pulsed load conditions such that
T ≈ T . The LTC3115E-1 is guaranteed to meet specifications from 0°C to
J
A
85°C junction temperature. Specifications over the –40°C to 125°C operating
31151f
3
LTC3115-1
ELECTRICAL CHARACTERISTICS
The junction temperature (T in °C) is calculated from the ambient
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: Switch timing measurements are made in an open-loop test
configuration. Timing in the application may vary somewhat from these
values due to differences in the switch pin voltage during the non-overlap
durations when switch pin voltage is influenced by the magnitude and
direction of the inductor current.
J
temperature (T in °C) and power dissipation (P in Watts) according to
A
D
the following formula:
T = T + (P • θ )
JA
J
A
D
where θ is the thermal impedance of the package.
JA
Note 3: Current measurements are performed when the LTC3115-1 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators.
(T = 25°C unless otherwise specified)
A
TYPICAL PERFORMANCE CHARACTERISTICS
PWM Mode Efficiency, VOUT = 5V,
fSW = 500kHz, Non-Bootstrapped
PWM Mode Efficiency,
PWM Mode Efficiency,
VOUT = 12V, fSW = 500kHz
VOUT = 24V, fSW = 500kHz
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
V
V
V
V
V
= 3.6V
= 5V
= 12V
= 24V
= 36V
IN
IN
IN
IN
IN
V
V
V
V
= 12V
= 18V
= 24V
= 36V
V
V
V
V
= 5V
IN
IN
IN
IN
IN
IN
IN
IN
= 12V
= 24V
= 36V
0.01
0.10
1
0.01
0.1
1
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
31151 G01
31151 G02
31151 G03
PWM Mode Efficiency, VOUT = 5V,
fSW = 1MHz, Non-Bootstrapped
PWM Mode Efficiency,
VOUT = 12V, fSW = 1MHz
PWM Mode Efficiency,
VOUT = 24V, fSW = 1MHz
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
V
V
V
V
V
= 3.6V
= 5V
= 12V
= 24V
= 36V
IN
IN
IN
IN
IN
V
V
V
V
= 5V
V
= 12V
= 18V
= 24V
= 36V
IN
IN
IN
IN
IN
IN
IN
IN
= 12V
= 24V
= 36V
V
V
V
0.01
0.1
1
0.01
0.1
1
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
31151 G04
31151 G05
31151 G06
31151f
4
LTC3115-1
(TA = 25°C unless otherwise specified)
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Efficiency, VOUT = 5V,
L = 15µH, Non-Bootstrapped
Burst Mode Efficiency,
VOUT = 12V, L = 15µH
Burst Mode Efficiency,
VOUT = 24V, L = 15µH
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
V
V
V
V
= 3.6V
= 12V
= 24V
= 36V
V
V
V
V
= 5V
V
V
V
V
= 12V
= 18V
= 24V
= 36V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 12V
= 24V
= 36V
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
31151 G07
31151 G08
31151 G09
Burst Mode No-Load Input
Current vs VIN
PWM Mode No-Load Input
Current vs VIN
Maximum Load Current
vs VIN, PWM Mode
400
350
300
250
200
150
100
50
50
45
40
35
30
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
0
f = 1MHz
SW
L = 22µH
V
V
V
V
= 24V
= 15V
= 5V
V
V
V
= 24V
= 12V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
f
= 500kHz
SW
= 5V, BOOTSTRAPPED
V
V
V
= 24V
= 12V
= 5V
OUT
OUT
OUT
0
0
2
10
INPUT VOLTAGE (V)
40
2
10
40
40
2
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
31151 G11
31151 G12
31151 G10
Maximum Load Current
vs VIN, PWM Mode
Maximum Load Current
vs VIN, PWM Mode
Maximum Load Current
vs VIN, Burst Mode Operation
1000
100
10
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
L = 22µH
L = 5.2µH
L = 15µH
f
= 2MHz
f
= 1MHz
SW
SW
V
V
V
= 32V
= 12V
= 5V
V
V
V
= 24V
= 12V
= 5V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
= 12V
= 5V
OUT
OUT
40
40
2
10
2
10
40
2
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
31151 G48
31151 G47
31151 G13
31151f
5
LTC3115-1
(TA = 25°C unless otherwise specified)
Combined VCC/PVCC Supply
TYPICAL PERFORMANCE CHARACTERISTICS
Combined VCC/PVCC Supply
Efficiency vs Switching Frequency
Current vs Switching Frequency
Current vs VCC
35
30
25
16
14
12
10
95
90
85
80
75
70
PWM MODE
L = 47µH
BOOTSTRAPPED
V
V
= 24V
IN
= 5V
OUT
LOAD
I
= 0.5A
f
= 1MHz
SW
V
OUT
= 36V
= 24V
IN
V
20
15
10
5
8
6
V
V
= 12V
= 5V
IN
OUT
f
= 500kHz
SW
NON-BOOTSTRAPPED
4
2
0
0
3
3.5
4.5
2.5
5
5.5
500
1000
2000
4
1000
SWITCHING FREQUENCY (kHz)
1500
0
1500
0
500
2000
V
(V)
SWITCHING FREQUENCY (kHz)
CC
31151 G16
31151 G15
31151 G14
Combined VCC/PVCC Supply
Current vs Temperature
Output Voltage Line Regulation
Output Voltage Load Regulation
0.5
0.4
12.0
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11.0
0.5
0.4
V
V
SW
= 6V
IN
OUT
= 5V
= 1MHz
f
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
10
20
30
40
–50
0
50
100
150
0
0.5
1
1.5
2
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD CURRENT (A)
31151 G19
31151 G17
31151 G18
VCC Voltage vs Temperature
VCC Regulator Line Regulation
VCC Regulator Load Regulation
1.0
0.8
1.0
0.8
0
–0.5
–1.0
–1.5
–2.0
–2.5
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
10
20
30
40
10
20
30
(mA)
40
50
–50
0
50
TEMPERATURE (°C)
100
150
0
INPUT VOLTAGE (V)
I
CC
31151 G22
31151 G21
31151 G20
31151f
6
LTC3115-1
(T = 25°C unless otherwise specified)
A
TYPICAL PERFORMANCE CHARACTERISTICS
RUN Pin Hysteresis Current
vs Temperature
VCC Regulator Dropout Voltage
vs Temperature
RUN Pin Threshold
vs Temperature
1.0
0.8
2.0
1.5
0.25
0.20
0.15
0.10
0.05
0
V
= 4V
= 20mA
IN
I
VCC
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
50
–50
0
100
150
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
31151 G25
31151 G24
31151 G23
Oscillator Frequency
vs Temperature
Oscillator Frequency vs RT
Oscillator Frequency vs VIN
2.0
1.5
10000
1000
100
2.0
1.5
f
= 1MHz
f
= 1MHz
SW
SW
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
–2.0
50
–50
0
100
150
10
100
(kΩ)
1000
2
10
(V)
40
TEMPERATURE (°C)
R
T
V
IN
31151 G26
31151 G27
31151 G28
Power Switch Resistance
vs Temperature
RUN Pin Current
vs RUN Pin Voltage
Shutdown Current on VIN/PVIN
vs Input Voltage
3.0
2.5
300
250
7
6
V
= 0V
V
IN
= 40V
RUN
5
2.0
1.5
200
150
4
3
2
1.0
0.5
0
100
50
0
1
0
–1
20
RUN PIN VOLTAGE (V)
0
10
30
40
–50
0
50
100
150
0
10
20
30
40
INPUT VOLTAGE (V)
TEMPERATURE (°C)
31151 G29
31151 G31
31151 G30
31151f
7
LTC3115-1
(TA = 25°C unless otherwise specified)
TYPICAL PERFORMANCE CHARACTERISTICS
Power Switch Resistance
vs VCC
Inductor Current Limit Thresholds
vs Temperature
FB Voltage vs Temperature
1.0
0.8
5
4
170
165
160
155
150
145
140
0.6
3
SWA
CURRENT
LIMIT
0.4
2
0.2
1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–4
–5
SWB
CURRENT
LIMIT
2.5
3.5
4
4.5
5
5.5
–50
0
50
TEMPERATURE (°C)
150
–50
0
50
TEMPERATURE (°C)
100
150
3
100
V
(V)
CC
31151 G32
31151 G33
31151 G34
SW1, SW2 Minimum Low Time
vs Temperature
SW1, SW2 Minimum Low Time
vs Switching Frequency
SW1, SW2 Minimum Low Time
vs VCC
180
160
140
120
100
80
110
108
106
104
102
100
98
200
180
160
f
= 1MHz
SW
NO LOAD
f
= 300kHz
SW
140
120
100
80
V
= 2.7V
CC
f
f
= 1MHz
= 2MHz
SW
SW
96
V
= 4.4V
CC
94
92
60
90
60
2.5
3.5
4
4.5
5
5.5
3
–50
0
50
100
150
500
1000
2000
0
1500
V
(V)
TEMPERATURE (°C)
CC
SWITCHING FREQUENCY (kHz)
31151 G36
31151 G35
31151 G37
SW2 Maximum Duty Cycle
vs Switching Frequency
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 750kHz
Die Temperature Rise vs Load
Current, VOUT = 5V, fSW = 1.5MHz
60
50
100
90
80
70
60
50
40
30
20
10
0
95
94
93
92
91
90
V
V
V
V
V
= 36V
= 24V
= 12V
= 6V
V
V
V
V
V
= 36V
= 24V
= 12V
= 6V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 3.6V
= 3.6V
40
30
20
10
0
STANDARD DEMO PCB
L = 15µH MSS1048
STANDARD DEMO PCB
L = 15µH MSS1048
2
0
500
1000
1500
0
0.5
1
1.5
2
0
0.5
1
1.5
2000
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
31151 G49
31151 G50
31151 G38
31151f
8
LTC3115-1
(T = 25°C unless otherwise specified)
A
TYPICAL PERFORMANCE CHARACTERISTICS
Die Temperature Rise vs Load
Current, VOUT = 12V, fSW = 750kHz
Load Transient (0A to 1A),
IN = 24V, VOUT = 5V
Load Transient (0A to 1A),
VIN = 3.6V, VOUT = 5V
V
80
70
60
50
40
30
20
10
0
LOAD
CURRENT
(1A/DIV)
V
V
V
V
= 36V
= 24V
= 12V
= 6V
LOAD
CURRENT
(1A/DIV)
IN
IN
IN
IN
V
V
OUT
OUT
(200mV/DIV)
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(2A/DIV)
31151 G39
31151 G40
FRONT PAGE
APPLICATION
200µs/DIV
FRONT PAGE
APPLICATION
200µs/DIV
STANDARD DEMO PCB
L = 15µH MSS1048
0
0.5
1
1.5
2
LOAD CURRENT (A)
31151 G51
Output Voltage Ripple in
Burst Mode Operation,
VIN = 24V, VOUT = 5V
Output Voltage Ripple in PWM
Mode, VIN = 24V, VOUT = 5V
Soft-Start Waveforms
V
RUN
INDUCTOR
CURRENT
(100mA/DIV)
(5V/DIV)
V
OUT
(50mV/DIV)
V
CC
(2V/DIV)
V
V
OUT
INDUCTOR
CURRENT
(0.5A/DIV)
OUT
(5mV/DIV)
(2V/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 G42
31151 G41
31151 G43
FRONT PAGE
APPLICATION
2ms/DIV
L = 15µH
20µs/DIV
1µs/DIV
C
I
= 22µF
= 22µF
OUT
= 25mA
LOAD
Burst Mode Operation to PWM
Mode Output Voltage Transient
Phase-Locked Loop Acquisition,
VIN = 24V 1.2MHz Clock
Phase-Locked Loop Release,
IN = 24V, 1.2MHz Clock
V
V
PWM/SYNC
(5V/DIV)
V
PWM/SYNC
(5V/DIV)
V
PWM/SYNC
(5V/DIV)
V
OUT
V
V
OUT
OUT
(200mV/DIV)
(200mV/DIV)
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 G45
31151 G46
31151 G44
FRONT PAGE
APPLICATION
50µs/DIV
FRONT PAGE
APPLICATION
50µs/DIV
FRONT PAGE
APPLICATION
500µs/DIV
31151f
9
LTC3115-1
PIN FUNCTIONS (DHD/FE)
RUN (Pin 1/Pin 2): Input to Enable and Disable the IC and
Set Custom Input UVLO Thresholds. The RUN pin can be
driven by an external logic signal to enable and disable
the IC. In addition, the voltage on this pin can be set by
a resistor divider connected to the input voltage in order
to provide an accurate undervoltage lockout threshold.
The IC is enabled if RUN exceeds 1.21V nominally. Once
enabled, a 0.5µA current is sourced by the RUN pin to
provide hysteresis. To continuously enable the IC, this pin
canbetieddirectlytotheinputvoltage.TheRUNpincannot
V
(Pin 9/Pin 12): Low Voltage Supply Input for IC Con-
CC
trol Circuitry. This pin powers internal IC control circuitry
and must be connected to the PV pin in the application.
CC
A 4.7µF or larger bypass capacitor should be connected
between this pin and ground. The V and PV pins must
CC
CC
be connected together in the application.
V (Pin10/Pin13):PowerSupplyConnectionforInternal
IN
Circuitry and the V Regulator. This pin provides power
CC
to the internal V regulator and is the input voltage sense
CC
connection for the V divider. A 0.1µF bypass capacitor
IN
be forced more than 0.3V above V under any condition.
IN
should be connected between this pin and ground. The
bypass capacitor should be located as close to the IC as
possible and should have a short return path to ground.
SW2 (Pin 2/Pin 3): Buck-Boost Converter Power Switch
Pin. This pin should be connected to one side of the buck-
boost inductor.
PV (Pin 11/Pin 14): Internal V Regulator Output. This
CC
CC
PV
(Pin3/Pin4):Buck-BoostConverterPowerOutput.
pin is the output pin of the internal linear regulator that
OUT
This pin should be connected to a low ESR capacitor with
a value of at least 10µF. The capacitor should be placed as
close to the IC as possible and should have a short return
generates the V rail from V . The PV pin is also the
CC
IN
CC
supply connection for the power switch gate drivers. If
the trace connecting PV to V cannot be made short in
CC
CC
path to ground. In applications with V
> 20V that are
length,anadditionalbypasscapacitorshouldbeconnected
OUT
subject to output overload or short-circuit conditions, it
is recommended that a Schottky diode be installed from
between this pin and ground. The V and PV pins must
CC
CC
be connected together in the application.
SW2 (anode) to PV
(cathode). In applications subject
OUT
BST2(Pin12/Pin15):FlyingCapacitorPinforSW2.Thispin
must beconnected to SW2 througha 0.1µFcapacitor. This
pinisusedtogeneratethegatedriverailforpowerswitchD.
to output short circuits through an inductive load, it is rec-
ommendedthataSchottkydiodebeinstalledfromground
(anode) to PV
(cathode) to limit the extent that PV
OUT
OUT
BST1(Pin13/Pin16):FlyingCapacitorPinforSW1.Thispin
must beconnected to SW1 througha 0.1µFcapacitor. This
pinisusedtogeneratethegatedriverailforpowerswitchA.
is driven below ground during the short-circuit transient.
GND (Pins 4, 5/Pins 5, 6): Signal Ground. These pins are
the ground connections for the control circuitry of the IC
and must be tied to ground in the application.
PV (Pin 14/Pin 17): Power Input for the Buck-Boost
IN
Converter. A 4.7µF or larger bypass capacitor should
be connected between this pin and ground. The bypass
capacitor should be located as close to the IC as possible
and should via directly down to the ground plane. When
powered through long leads or from a high ESR power
source, a larger bulk input capacitor (typically 47µF to
100µF) may be required.
VC (Pin 6/Pin 7): Error Amplifier Output. A frequency
compensation network must be connected between this
pin and FB to stabilize the voltage control loop.
FB(Pin7/Pin8):FeedbackVoltageInput.Aresistordivider
connected to this pin sets the output voltage for the buck-
boost converter. The nominal FB voltage is 1000mV. Care
should be taken in the routing of connections to this pin in
order to minimize stray coupling to the switch pin traces.
SW1(Pin15/Pin18):Buck-BoostConverterPowerSwitch
Pin. This pin should be connected to one side of the buck-
boost inductor.
RT (Pin 8/Pin 9): Oscillator Frequency Programming Pin.
A resistor placed between this pin and ground sets the
switching frequency of the buck-boost converter.
31151f
10
LTC3115-1
PIN FUNCTIONS (DHD/FE)
PWM/SYNC (Pin 16/Pin 19): Burst Mode/PWM Mode
Control Pin and Synchronization Input. Forcing this pin
highcausestheICtooperateinfixedfrequencyPWMmode
at all loads using the internal oscillator at the frequency
set by the RT Pin. Forcing this pin low places the IC into
Burst Mode operation for improved efficiency at light load
and reduced standby current. If an external clock signal
is connected to this pin, the buck-boost converter will
synchronize its switching with the external clock using
fixed frequency PWM mode operation. The pulse width
(negative or positive) of the applied clock should be at
least 100ns.
PGND (Exposed Pad Pin 17/Pins 1, 10, 11, 20, Ex-
posed Pad Pin 21): Power Ground Connections. These
pins should be connected to the power ground in the
application. The exposed pad in the DHD package is the
power ground connection. It must be soldered to the
PCB and electrically connected to ground through the
shortest and lowest impedance connection possible. For
optimal thermal performance, the exposed pad should
be connected to the PCB ground plane in both the DHD
and FE packages.
Pin numbers are shown for the DHD package only.
BLOCK DIAGRAM
14
15
SW1
2
3
10
PV
SW2
PV
V
IN
IN
OUT
3A
CURRENT
LIMIT
+
–
A
D
REVERSE
BLOCKING
LDO
PV
*
CC
11
REVERSE
CURRENT
LIMIT
+
B
C
–1.5A
0A
–
PGND PGND
ZERO
CURRENT
+
–
GATE
DRIVES
BST2
BST1
12
13
V
CC
V
*
CC
1.21V
BANDGAP
REFERENCE
9
1000mV
VC
FB
V
IN
6
7
+
–
V
INPUT UVLO
IN
–
+
2.4V
1000mV
+
÷
PWM
V
IN
SOFT-START
RAMP
0.5µA
RT
OSCILLATOR
8
PWM/SYNC
RUN
16
+
–
1
BURST/PWM
(PWM MODE IF PWM/SYNC
IS HIGH OR SWITCHING)
CHIP
ENABLE
MODE
SELECTION
1.21V
V
+
–
CC
UVLO
2.4V
EXPOSED
PAD
OVERTEMPERATURE
GND GND
PGND
5
4
17
3115 BD
*PV AND V MUST BE CONNECTED TOGETHER IN THE APPLICATION
CC CC
THE EXPOSED PAD IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED
TO THE BOARD AND ELECTRICALLY CONNECTED TO GROUND
31151f
11
LTC3115-1
OPERATION
INTRODUCTION
switching spectrum. A proprietary switching algorithm
provides seamless transitions between operating modes
and eliminates discontinuities in the average inductor cur-
rent, inductor current ripple, and loop transfer function
throughout all regions of operation. These advantages
result in increased efficiency, improved loop stability, and
loweroutputvoltagerippleincomparisontothetraditional
4-switch buck-boost converter.
The LTC3115-1 is a monolithic buck-boost converter that
can operate with input and output voltages from as low
as 2.7V to as high as 40V. Four internal low resistance N-
channelDMOSswitchesminimizethesizeoftheapplication
circuit and reduce power losses to maximize efficiency.
Internal high side gate drivers, which require only the
addition of two small external capacitors, further simplify
thedesignprocess.Aproprietaryswitchcontrolalgorithm
allows the buck-boost converter to maintain output volt-
age regulation with input voltages that are above, below
or equal to the output voltage. Transitions between these
operating modes are seamless and free of transients and
subharmonicswitching.TheLTC3115-1canbeconfigured
tooperateoverawiderangeofswitchingfrequencies,from
100kHzto2MHz, allowingapplicationstobeoptimizedfor
boardareaandefficiency. Withitsconfigurabilityandwide
operating voltage range, the LTC3115-1 is ideally suited to
a wide range of power systems especially those requiring
compatibility with a variety of input power sources such
as lead-acid batteries, USB ports, and industrial supply
rails as well as from power sources which have wide or
poorly controlled voltage ranges such as FireWire and
unregulated wall adapters.
Figure1showsthetopologyoftheLTC3115-1powerstage
whichiscomprisedoffourN-channelDMOSswitchesand
theirassociatedgatedrivers.InPWMmodeoperationboth
switch pins transition on every cycle independent of the
input and output voltage. In response to the error ampli-
fier output, an internal pulse width modulator generates
the appropriate switch duty cycles to maintain regulation
of the output voltage.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for the minimum switch low duration (typically 100ns).
DuringtheswitchlowdurationswitchCisturnedonwhich
, to
forces SW2 low and charges the flying capacitor, C
BST2
ensure that the voltage of the switch D gate driver supply
rail is maintained. The duty cycle of switches A and B are
adjusted to provide the appropriate buck mode duty cycle.
The LTC3115-1 has an internal fixed-frequency oscillator
with a switching frequency that is easily set by a single
external resistor. In noise sensitive applications, the con-
verter can also be synchronized to an external clock via
the PWM/SYNC pin. The LTC3115-1 has been optimized
to reduce input current in shutdown and standby for ap-
plications which are sensitive to quiescent current draw,
such as battery-powered devices. In Burst Mode opera-
tion, the no-load standby current is only 50µA (typical)
and in shutdown the total supply current is reduced to
3µA (typical).
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A remains on
for the entire switching cycle except for the minimum
switch low duration (typically 100ns) while switches C
and D are modulated to maintain the required boost mode
C
BST1
C
BST2
L
BST1
PV
A
SW1
SW2 PV
BST2
IN
OUT
PV
PV
CC
CC
PWM MODE OPERATION
D
LTC3115-1
With the PWM/SYNC pin forced high or driven by an ex-
ternal clock, the LTC3115-1 operates in a fixed-frequency
pulsewidthmodulation(PWM)modeusingavoltagemode
controlloop.Thismodeofoperationmaximizestheoutput
current that can be delivered by the converter, reduces
outputvoltageripple,andyieldsalownoisefixed-frequency
PV
PV
CC
CC
B
C
PGND
PGND
31151 F01
Figure 1. Power Stage Schematic
31151f
12
LTC3115-1
OPERATION
V
dutycycle.Theminimumswitchlowdurationensuresthat
OUT
LTC3115-1
V
IN
flying capacitor C
is charged sufficiently to maintain
R
BST1
FF
the voltage on the BST1 rail.
R
R
1000mV
FB
+
–
TOP
BOT
C
FF
÷
PWM
Oscillator and Phase-Locked Loop
VC
31151 F02
C
The LTC3115-1 operates from an internal oscillator with a
switching frequency that is configured by a single external
resistor between the RT pin and ground. For noise sensi-
tive applications, an internal phase-locked loop allows
the LTC3115-1 to be synchronized to an external clock
signal applied to the PWM/SYNC pin. The phase-locked
loop is only able to increase the frequency of the internal
FB
R
FB
C
POLE
Figure 2. Error Amplifier and Compensation Network
network in LTC3115-1 applications can be found in the
Applications Information section of this data sheet.
oscillator to obtain synchronization. Therefore, the R
T
resistor must be chosen to program the internal oscilla-
tor to a lower frequency than the frequency of the clock
applied to the PWM/SYNC pin. Sufficient margin must
be included to account for the frequency variation of the
external synchronization clock as well as the worst-case
variation in frequency of the internal oscillator. Whether
operating from its internal oscillator or synchronized to an
externalclocksignal,theLTC3115-1isabletooperatewith
a switching frequency from 100kHz to 2MHz, providing
the ability to minimize the size of the external components
and optimize the power conversion efficiency.
Inductor Current Limits
The LTC3115-1 has two current limit circuits that are
designed to limit the peak inductor current to ensure that
the switch currents remain within the capabilities of the
IC during output short-circuit or overload conditions.
The primary inductor current limit operates by injecting
a current into the feedback pin which is proportional to
the extent that the inductor current exceeds the current
limit threshold (typically 3A). Due to the high gain of
the feedback loop, this injected current forces the error
amplifier output to decrease until the average current
through the inductor is approximately reduced to the
current limit threshold. This current limit circuit maintains
the error amplifier in an active state to ensure a smooth
recovery and minimal overshoot once the current limit
fault condition is removed. However, the reaction speed
of this current limit circuit is limited by the dynamics of
the error amplifier. On a hard output short, it is possible
for the inductor current to increase substantially beyond
the current limit threshold before the average current limit
has time to react and reduce the inductor current. For this
reason, there is a second current limit circuit which turns
off power switch A if the current through switch A exceeds
approximately 160% of the primary inductor current limit
threshold.Thisprovidesadditionalprotectioninthecaseof
an instantaneous hard output short and provides time for
Error Amplifier and V Divider
IN
The LTC3115-1 has an internal high gain operational
amplifier which provides frequency compensation of the
control loop that maintains output voltage regulation. To
ensurestabilityofthiscontrolloop,anexternalcompensa-
tion network must be installed in the application circuit.
A Type III compensation network as shown in Figure 2 is
recommended for most applications since it provides the
flexibility to optimize the converter’s transient response
while simultaneously minimizing any DC error in the
output voltage.
As shown in Figure 2, the error amplifier is followed by
an internal analog divider which adjusts the loop gain by
the reciprocal of the input voltage in order to minimize
loop-gain variation over changes in the input voltage.
This simplifies design of the compensation network and
optimizes the transient response over the entire range of
input voltages. Details on designing the compensation
falls
the primary current limit to react. In addition, if V
below1.85V,theinductorcurrentlimitisfoldedbacktohalf
its nominal value in order to minimize power dissipation.
OUT
31151f
13
LTC3115-1
OPERATION
Reverse Current Limit
Burst Mode OPERATION
In PWM mode operation, the LTC3115-1 synchronously
switches all four power devices. As a result, in addition to
being able to supply current to the output, the converter
has the ability to actively conduct current away from the
output if that is necessary to maintain regulation. If the
output is held above regulation, this could result in large
reverse currents. This situation can occur if the output of
the LTC3115-1 is held up momentarily by another supply
asmayoccurduringapower-uporpower-downsequence.
To prevent damage to the part under such conditions, the
LTC3115-1hasareversecurrentcomparatorthatmonitors
the current entering power switch D from the load. If this
current exceeds 1.5A (typical) switch D is turned off for
theremainderoftheswitchingcycleinordertopreventthe
reverse inductor current from reaching unsafe levels.
When the PWM/SYNC pin is held low, the buck-boost
converter employs Burst Mode operation using a vari-
able frequency switching algorithm that minimizes the
no-load input quiescent current and improves efficiency
at light load by reducing the amount of switching to the
minimum level required to support the load. The output
current capability in Burst Mode operation is substantially
lower than in PWM mode and is intended to support light
standby loads (typically under 50mA). Curves showing
the maximum Burst Mode load current as a function of
the input and output voltage can be found in the Typical
Characteristics section of this data sheet. If the converter
load in Burst Mode operation exceeds the maximum Burst
Mode current capability, the output will lose regulation.
Each Burst Mode cycle is initiated when switches A and
C turn on producing a linearly increasing current through
the inductor. When the inductor current reaches the Burst
Mode current limit (1A typically) switches B and D are
turned on, discharging the energy stored in the inductor
into the output capacitor and load. Once the inductor
current reaches zero, all switches are turned off and the
cycleiscomplete.Currentpulsesgeneratedinthismanner
are repeated as often as necessary to maintain regulation
of the output voltage. In Burst Mode operation, the error
amplifier is not used but is instead placed in a low current
standby mode to reduce supply current and improve light
load efficiency.
Output Current Capability
The maximum output current that can be delivered by the
LTC3115-1 is dependent upon many factors, the most
significant being the input and output voltages. For V
OUT
= 5V and V ≥ 3.6V, the LTC3115-1 is able to support up
IN
to a 1A load continuously. For V
= 12V and V ≥ 12V,
OUT
IN
the LTC3115-1 is able to support up to a 2A load continu-
ously. Typically, the output current capability is greatest
whentheinputvoltageisapproximatelyequaltotheoutput
voltage. At larger step-up voltage ratios, the output cur-
rent capability is reduced because the lower duty cycle of
switch D results in a larger inductor current being needed
to support a given load. Additionally, the output current
capability generally decreases at large step-down voltage
ratios due to higher inductor current ripple which reduces
the maximum attainable inductor current.
SOFT-START
To minimize input current transients on power-up, the
LTC3115-1 incorporates an internal soft-start circuit with
a nominal duration of 9ms. The soft-start is implemented
by a linearly increasing ramp of the error amplifier refer-
ence voltage during the soft-start duration. As a result,
the duration of the soft-start period is largely unaffected
by the size of the output capacitor or the output regula-
tion voltage. Given the closed-loop nature of the soft-start
implementation, the converter is able to respond to load
transients that occur during the soft-start interval. The
soft-start period is reset by thermal shutdown and UVLO
The output current capability can also be affected by
inductor characteristics. An inductor with large DC resis-
tance will degrade output current capability, particularly
in boost mode operation. Larger value inductors generally
maximize output current capability by reducing inductor
current ripple. In addition, higher switching frequencies
(especiallyabove750kHz)willreducethemaximumoutput
current that can be supplied (see the Typical Performance
Characteristics for details).
and V .
events on both V
IN
CC
31151f
14
LTC3115-1
OPERATION
V
REGULATOR
input and output voltages. As a result, at higher switching
frequencies and higher input and output voltages the
CC
CC
An internal low dropout regulator generates the 4.45V
(nominal) V rail from V . The V rail powers the in-
V
regulator dropout voltage will increase, making it
CC
IN
CC
more likely that the V UVLO threshold could become
CC
ternal control circuitry and power device gate drivers of
the limiting factor. Curves provided in the Typical Perfor-
the LTC3115-1. The V regulator is disabled in shutdown
CC
mance Characteristics section of this data sheet show the
to reduce quiescent current and is enabled by forcing the
typical V current and can be used to estimate the V
CC
CC
RUN pin above its logic threshold. The V regulator in-
CC
regulator dropout voltage in a particular application. In
cludes current limit protection to safeguard against short
applications where V is bootstrapped (powered by V
CC
OUT
circuiting of the V rail. For applications where the output
CC
or by an auxiliary supply rail through a Schottky diode)
the minimum input operating voltage will be limited only
by the input voltage UVLO threshold.
voltage is set to 5V, the V rail can be driven from the
CC
outputrailthroughaSchottkydiode. Bootstrappinginthis
manner can provide a significant efficiency improvement,
particularly at large voltage step down ratios, and may
also allow operation down to a lower input voltage. The
RUN PIN COMPARATOR
In addition to serving as a logic-level input to enable the
IC, the RUN pin features an accurate internal compara-
tor allowing it to be used to set custom rising and falling
input undervoltage lockout thresholds with the addition
of an external resistor divider. When the RUN pin is driven
maximum operating voltage for the V pin is 5.5V. When
CC
forcing V externally, care must be taken to ensure that
CC
this limit is not exceeded.
UNDERVOLTAGE LOCKOUT
above its logic threshold (typically 0.8V) the V regulator
CC
To eliminate erratic behavior when the input voltage is
too low to ensure proper operation, the LTC3115-1 incor-
porates internal undervoltage lockout (UVLO) circuitry.
is enabled which provides power to the internal control
circuitry of the IC and the accurate RUN pin comparator is
enabled. If the RUN pin voltage is increased further so that
itexceedstheRUNcomparatorthreshold(1.21Vnominal),
the buck-boost converter will be enabled.
There are two UVLO comparators, one that monitors V
IN
and another that monitors V . The buck-boost converter
CC
is disabled if either V or V falls below its respective
IN
CC
If the RUN pin is brought below the RUN comparator
threshold, the buck-boost converter will inhibit switching,
UVLO threshold. The input voltage UVLO comparator has
a falling threshold of 2.4V (typical). If the input voltage
fallsbelowthislevelallswitchingisdisableduntiltheinput
but the V regulator and control circuitry will remain
CC
powered unless the RUN pin is brought below its logic
threshold. Therefore, in order to place the part in shut-
down and reduce the input current to its minimum level
(3µA typical) it is necessary to ensure that the RUN pin
is brought below the worst-case logic threshold (0.3V).
The RUN pin is a high voltage input and can be connected
voltage rises above 2.6V (nominal). The V UVLO has a
CC
falling threshold of 2.4V. If V falls below this threshold
CC
thebuck-boostconverterispreventedfromswitchinguntil
V
CC
rises above 2.6V.
Depending on the particular application circuit it is pos-
sible that either of these UVLO thresholds could be the
factor limiting the minimum input operating voltage of the
LTC3115-1. The dominant factor depends on the voltage
drop between V and V which is determined by the
directly to V to continuously enable the part when the
IN
input supply is present. If the RUN pin is forced above
approximately 5V it will sink a small current as given by
the following equation:
IN
CC
CC
dropout voltage of the V regulator and is proportional
VRUN –5V
to the total load current drawn from V . The load cur-
IRUN
≅
CC
5MΩ
rent on the V regulator is principally generated by the
CC
gate driver supply currents which are proportional to
With the addition of an external resistor divider as shown
in Figure 3, the RUN pin can be used to establish a custom
operating frequency and generally increase with larger
31151f
15
LTC3115-1
OPERATION
THERMAL CONSIDERATIONS
V
CC
LTC3115-1
The power switches in the LTC3115-1 are designed to op-
erate continuously with currents up to the internal current
limit thresholds. However, when operating at high current
levels there may be significant heat generated within the
0.5µA
V
IN
1.21V
–
+
R1
ENABLE
RUN
SWITCHING
IC. In addition, in many applications the V regulator is
CC
ENA
operated with large input-to-output voltage differentials
resulting in significant levels of power dissipation in its
passelementwhichcanaddsignificantlytothetotalpower
dissipated within the IC. As a result, careful consideration
mustbegiventothethermalenvironmentoftheICinorder
to optimize efficiency and ensure that the LTC3115-1 is
able to provide its full-rated output current. Specifically,
the exposed die attach pad of both the DHD and FE pack-
ages should be soldered to the PC board and the PC board
shouldbedesignedtomaximizetheconductionofheatout
of the IC package. This can be accomplished by utilizing
multiple vias from the die attach pad connection to other
PCB layers containing a large area of exposed copper.
ENABLE
R2
+
–
V
REGULATOR AND
CC
0.8V
CONTROL CIRCUITS
INPUT LOGIC
THRESHOLD
31151 F03
Figure 3. Accurate RUN Pin Comparator
inputundervoltagelockoutthreshold.Thebuck-boostcon-
verter is enabled when the RUN pin reaches 1.21V which
allows the rising UVLO threshold to be set via the resis-
tor divider ratio. Once the RUN pin reaches the threshold
voltage, the comparator switches and the buck-boost
converter is enabled. In addition, an internal 0.5µA (typi-
cal) current source is enabled which sources current out
of the RUN pin raising the RUN pin voltage away from
If the die temperature exceeds approximately 165°C, the
IC will enter overtemperature shutdown and all switching
will be inhibited. The part will remain disabled until the
die cools by approximately 10°C. The soft-start circuit is
re-initialized in overtemperature shutdown to provide a
smooth recovery when the fault condition is removed.
the threshold. In order to disable the part, V must be
IN
reduced sufficiently to overcome the hysteresis generated
by this current as well as the 100mV hysteresis of the RUN
comparator. As a result, the amount of hysteresis can be
independently programmed without affecting the rising
UVLO threshold by scaling the values of both resistors.
31151f
16
LTC3115-1
APPLICATIONS INFORMATION
ThestandardLTC3115-1applicationcircuitisshownasthe
typical application on the front page of this data sheet. The
appropriateselectionofexternalcomponentsisdependent
upon the required performance of the IC in each particular
application given considerations and trade-offs such as
PCB area, cost, output and input voltage, allowable ripple
voltage,efficiencyandthermalconsiderations.Thissection
of the data sheet provides some basic guidelines and con-
siderations to aid in the selection of external components
and the design of the application circuit.
have a greater series resistance, thereby counteracting
this efficiency advantage. In general, inductors with larger
inductance values and lower DC resistance will increase
the deliverable output current and improve the efficiency
of LTC3115-1 applications.
An inductor used in LTC3115-1 applications should have a
saturationcurrentratingthatisgreaterthantheworst-case
average inductor current plus half the ripple current. The
peak-to-peak inductor current ripple for each operational
modecanbecalculatedfromthefollowingformula, where
f is the switching frequency, L is the inductance, and
V
Capacitor Selection
CC
t
is the switch pin minimum low time. The switch pin
LOW
The V output on the LTC3115-1 is generated from the
minimum low time can be determined from curves given
in the Typical Performance Characteristics section of this
data sheet.
CC
input voltage by an internal low dropout regulator. The V
CC
regulator has been designed for stable operation with a
wide range of output capacitors. For most applications,
a low ESR ceramic capacitor of at least 4.7µF should be
utilized. The capacitor should be placed as close to the
VOUT V – V
1
f
IN
OUT
∆IL(P-P)(BUCK)
=
– t
LOW
L
V
IN
pin as possible and should connect to the PV pin and
CC
V
L
VOUT – V
1
IN
IN
ground through the shortest traces possible. The PV
∆IL(P-P)(BOOST )
=
– t
CC
f
LOW
VOUT
pin is the regulator output and is also the internal supply
pin for the gate drivers and boost rail charging diodes.
Inadditiontoitsinfluenceonpowerconversionefficiency,
the inductor DC resistance can also impact the maximum
output current capability of the buck-boost converter par-
ticularly at low input voltages. In buck mode, the output
current of the buck-boost converter is generally limited
only by the inductor current reaching the current limit
threshold. However, in boost mode, especially at large
step-up ratios, the output current capability can also be
limited by the total resistive losses in the power stage.
These include switch resistances, inductor resistance,
and PCB trace resistance. Use of an inductor with high DC
resistance can degrade the output current capability from
thatshownintheTypicalPerformanceCharacteristicssec-
tion of this data sheet. As a guideline, in most applications
the inductor DC resistance should be significantly smaller
than the typical power switch resistance of 150mΩ.
The V pin is the supply connection for the remainder
CC
of the control circuitry. The PV and V pins must be
CC
CC
connected together on the application PCB. If the trace
connecting V to PV cannot be made via a short con-
CC
CC
nection, an additional 0.1µF bypass capacitor should be
placed between the V pin and ground using the shortest
CC
connections possible.
Inductor Selection
The choice of inductor used in LTC3115-1 application
circuits influences the maximum deliverable output cur-
rent, the magnitude of the inductor current ripple, and
the power conversion efficiency. The inductor must have
low DC series resistance or output current capability and
efficiency will be compromised. Larger inductance values
reduce inductor current ripple and will therefore gener-
ally yield greater output current capability. For a fixed DC
resistance, a larger value of inductance will yield higher
efficiency by reducing the peak current to be closer to the
average output current and therefore minimize resistive
losses due to high RMS currents. However, a larger induc-
tor value within any given inductor family will generally
Differentinductorcorematerialsandstyleshaveanimpact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
Thechoiceofinductorstyledependsupontheprice,sizing,
and EMI requirements of a particular application. Table 1
31151f
17
LTC3115-1
APPLICATIONS INFORMATION
provides a small sampling of inductors that are well suited
to many LTC3115-1 applications.
capacitance,t
LOAD
istheswitchpinminimumlowtime,and
LOW
I
is the output current. Curves for the value of t
LOW
as a function of switching frequency and temperature can
be found in Typical Performance Characteristics section
of this data sheet.
In applications with V
≥ 20V, it is recommended that
OUT
a minimum inductance value, L , be utilized where f is
MIN
the switching frequency:
ILOAD LOW
t
12H
f /Hz
∆VP-P(BUCK)
=
LMIN
=
COUT
(
)
IN
ILOAD VOUT – V + tLOWfV
IN
∆VP-P(BOOST)
=
Table 1. Representative Surface Mount Inductors
fC
VOUT
OUT
VALUE DCR
(µH) (mΩ) CURRENT (A)
MAX DC
SIZE (mm)
W × L × H
PART NUMBER
Theoutputvoltagerippleincreaseswithloadcurrentandis
generally higher in boost mode than in buck mode. These
expressionsonlytakeintoaccounttheoutputvoltageripple
that results from the output current being discontinuous.
They provide a good approximation to the ripple at any
significant load current but underestimate the output volt-
age ripple at very light loads where output voltage ripple
is dominated by the inductor current ripple.
Coilcraft
LPS6225
LPS6235
MSS1038
D03316P
4.7
6.8
22
65
75
70
50
3.2
2.8
3.3
3.0
6.2 × 6.2 × 2.5
6.2 × 6.2 × 3.5
10.2 × 10.5 × 3.8
12.9 × 9.4 × 5.2
15
Cooper-Bussmann
CD1-150-R
DR1030-100-R
FP3-8R2-R
DR1040-220-R
15
10
8.2
22
50
40
74
54
3.6
3.18
3.4
10.5 × 10.4 × 4.0
10.3 × 10.5 × 3.0
7.3 × 6.7 × 3.0
2.9
10.3 × 10.5 × 4.0
Panasonic
ELLCTV180M
ELLATV100M
In addition to output voltage ripple generated across the
output capacitance, there is also output voltage ripple
produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is
proportionaltotheseriesresistanceoftheoutputcapacitor
18
10
30
23
3.0
3.3
12 × 12 × 4.2
10 × 10 × 4.2
Sumida
CDRH8D28/HP
CDR10D48MNNP
CDRH8D28NP
10
39
4.7
78
105
24.7
3.0
3.0
3.4
8.3 × 8.3 × 3
10.3 × 10.3 × 5
8.3 × 8.3 × 3
and is given by the following expressions where R
is
ESR
Taiyo-Yuden
NR10050T150M
15
46
3.6
9.8 × 9.8 × 5
the series resistance of the output capacitor and all other
terms are as previously defined.
TOKO
B1047AS-6R8N
B1179BS-150M
892NAS-180M
6.8
15
18
36
56
42
2.9
3.3
3.0
7.6 × 7.6 × 5
10.3 × 10.3 × 4
12.3 × 12.3 × 4.5
ILOAD ESR
R
∆VP-P(BUCK)
=
≅ ILOADRESR
1– tLOW
f
Würth
7447789004
744771133
744066150
4.7
33
15
33
49
40
2.9
2.7
3.2
7.3 × 7.3 × 3.2
12 × 12 × 6
10 × 10 × 3.8
ILOAD ESR OUT
R
V
VOUT
∆VP-P(BOOST)
=
≅ ILOADRESR
V 1– t
f
V
(
)
IN
IN
LOW
Input Capacitor Selection
Output Capacitor Selection
The PV pin carries the full inductor current and provides
A low ESR output capacitor should be utilized at the buck-
boostconverteroutputinordertominimizeoutputvoltage
ripple.Multilayerceramiccapacitorsareanexcellentoption
as they have low ESR and are available in small footprints.
The capacitor value should be chosen large enough to
reduce the output voltage ripple to acceptable levels.
Neglecting the capacitor ESR and ESL, the peak-to-peak
output voltage ripple can be calculated by the following
IN
power to internal control circuits in the IC. To minimize
input voltage ripple and ensure proper operation of the IC,
a low ESR bypass capacitor with a value of at least 4.7µF
should be located as close to this pin as possible. The
traces connecting this capacitor to PV and the ground
IN
plane should be made as short as possible. The V pin
IN
provides power to the V regulator and other internal
CC
circuitry. If the PCB trace connecting V to PV is long, it
formulas, where f is the switching frequency, C
is the
IN
IN
OUT
31151f
18
LTC3115-1
APPLICATIONS INFORMATION
may be necessary to add an additional small value bypass
Table 2. Representative Bypass and Output Capacitors
capacitor near the V pin.
MANUFACTURER,
PART NUMBER
VALUE VOLTAGE
SIZE L × W × H (mm),
IN
(µF)
(V)
TYPE, ESR
When powered through long leads or from a high ESR
power source, a larger value bulk input capacitor may be
required.Insuchapplications,a47µFto100µFelectrolytic
capacitorinparallelwitha1µFceramiccapacitorgenerally
yields a high performance, low cost solution.
AVX
12103D226MAT2A
22
22
25
50
3.2 × 2.5 × 2.79
X5R Ceramic
TPME226K050R0075
7.3 × 4.3 × 4.1
Tantalum, 75mΩ
Kemet
C2220X226K3RACTU
22
22
25
16
5.7 × 5.0 × 2.4
Recommended Input and Output Capacitors
X7R Ceramic
The capacitors used to filter the input and output of the
LTC3115-1 must have low ESR and must be rated to
handle the large AC currents generated by switching con-
verters. This is important to maintain proper functioning
of the IC and to reduce output voltage ripple. There are
many capacitor types that are well suited to such appli-
cations including multilayer ceramic, low ESR tantalum,
OS-CON and POSCAP technologies. In addition, there
are certain types of electrolytic capacitors such as solid
aluminum organic polymer capacitors that are designed
for low ESR and high AC currents and these are also well
suited to LTC3115-1 applications (Table 2). The choice of
capacitor technology is primarily dictated by a trade-off
between cost, size and leakage current. Notice that some
capacitorssuchastheOS-CONandPOSCAPtechnologies
canexhibitsignificantDCleakagecurrentswhichmaylimit
their applicability in devices which require low no-load
quiescent current in Burst Mode operation.
A700D226M016ATE030
7.3 × 4.3 × 2.8
Alum. Polymer, 30mΩ
Murata
GRM32ER71E226KE15L
22
82
22
25
25
25
3.2 × 2.5 × 2.5
X7R Ceramic
Nichicon
PLV1E121MDL1
8 × 8 × 12
Alum. Polymer, 25mΩ
Panasonic
ECJ-4YB1E226M
3.2 × 2.5 × 2.5
X5R Ceramic
Sanyo
25TQC22MV
22
100
47
25
16
25
7.3 × 4.3 × 3.1
POSCAP, 50mΩ
16TQC100M
25SVPF47M
7.3 × 4.3 × 1.9
POSCAP, 45mΩ
6.6 × 6.6 × 5.9
OS-CON, 30mΩ
Taiyo Yuden
UMK325BJ106MM-T
10
22
50
25
3.2 × 2.5 × 2.5
X5R Ceramic
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR, and
low leakage currents. However, many ceramic capacitors
designed for power applications experience significant
loss in capacitance from their rated value with increased
DC bias voltages. For example, it is not uncommon for
a small surface mount ceramic capacitor to lose more
than 50% of its rated capacitance when operated near its
rated voltage. As a result, it is sometimes necessary to
use a larger value capacitance or a capacitor with a higher
voltage rating than required in order to actually realize the
intendedcapacitanceatthefulloperatingvoltage.Toensure
that the intended capacitance is realized in the application
circuit, be sure to consult the capacitor vendor’s curve of
capacitance versus DC bias voltage.
TMK325BJ226MM-T
3.2 × 2.5 × 2.5
X5R Ceramic
TDK
KTJ500B226M55BFT00
22
10
47
50
50
25
6.0 × 5.3 × 5.5
X7R Ceramic
C5750X7R1H106M
CKG57NX5R1E476M
5.7 × 5.0 × 2.0
X7R Ceramic
6.5 × 5.5 × 5.5
X5R Ceramic
Vishay
94SVPD476X0035F12
47
35
10.3 × 10.3 × 12.6
OS-CON, 30mΩ
31151f
19
LTC3115-1
APPLICATIONS INFORMATION
Programming Custom Input UVLO Thresholds
to 2MΩ). In such cases, the amount of hysteresis can be
increased further through the addition of an additional
With the addition of an external resistor divider connected
to the input voltage as shown in Figure 4, the RUN pin
can be used to program the input voltage at which the
LTC3115-1 is enabled and disabled.
resistor, R , as shown in Figure 5.
H
When using the additional R resistor, the rising RUN pin
H
threshold remains as given by the original equation and
the hysteresis is given by the following expression:
For a rising input voltage, the LTC3115-1 is enabled when
V reaches the threshold given by the following equation,
R1+ R2
RHR2+ RHR1+ R1R2
IN
VHYST
=
0.1V+
0.5µA
(
)
where R1 and R2 are the values of the resistor divider
R2
R2
resistors:
R1+ R2
V
IN
VTH(RISING) = 1.21V
R2
LTC3115-1
RUN
R1
R
H
To ensure robust operation in the presence of noise, the
RUN pin has two forms of hysteresis. A fixed 100mV of
hysteresis within the RUN pin comparator provides a
minimum RUN pin hysteresis equal to 8.3% of the input
turn-on voltage independent of the resistor divider values.
In addition, an internal hysteresis current that is sourced
from the RUN pin during operation generates an additive
level of hysteresis which can be programmed by the value
of R1 to increase the overall hysteresis to suit the require-
ments of specific applications.
R2
GND
3115 F05
Figure 5. Increasing Input UVLO hysteresis
ToimprovethenoiserobustnessandaccuracyoftheUVLO
thresholds, the RUN pin input can be filtered by adding a
1000pFcapacitorfromRUNtoGND.Largervaluedcapaci-
tors should not be utilized because they could interfere
with operation of the hysteresis.
Once the IC is enabled, it will remain enabled until the
inputvoltagedropsbelowthecomparatorthresholdbythe
Bootstrapping the V Regulator
CC
hysteresis voltage, V
, as given by the following equa-
HYST
tion where R1 and R2 are values of the divider resistors:
Thehighandlowsidegatedriversarepoweredthroughthe
PV railwhichisgeneratedfromtheinputvoltagethrough
CC
R1+ R2
VHYST = R1•0.5µA +
0.1V
aninternallinearregulator.Insomeapplications,especially
R2
at higher operating frequencies and high input and output
voltages, the power dissipation in the linear V regulator
CC
Therefore, the rising UVLO threshold and amount of
hysteresis can be independently programmed via appro-
priate selection of resistors R1 and R2. For high levels
of hysteresis, the value of R1 can become larger than is
desirable in a practical implementation (greater than 1MΩ
can become a key factor in the conversion efficiency of
the converter and can even become a significant source
of thermal heating. For example, at a 1.2MHz switching
frequency,aninputvoltageof36V,andanoutputvoltageof
24V, the total PV /V current is approximately 18mA as
CC CC
V
IN
shown in the Typical Performance Characteristics section
of this data sheet. As a result, this will generate 568mW of
LTC3115-1
RUN
R1
R2
power dissipation in the V regulator which will result in
CC
anincreaseindietemperatureofapproximately24°above
ambient in the DFN package. This significant power loss
will have a substantial impact on the conversion efficiency
andtheadditionalheatingmaylimitthemaximumambient
GND
31151 F04
Figure 4. Setting the Input UVLO Threshold and Hysteresis
operating temperature for the application.
31151f
20
LTC3115-1
APPLICATIONS INFORMATION
A significant performance advantage can be attained in
applications which have the converter output voltage pro-
grammed to 5V if the output voltage is utilized to power
The gain term, G
, is comprised of three different
BUCK
components: the gain of the analog divider, the gain of the
pulse width modulator, and the gain of the power stage as
the PV and V rails. This can be done by connecting a
given by the following expressions where V is the input
CC
CC
IN
SchottkydiodefromV toPV /V asshowninFigure 6.
voltage to the converter, f is the switching frequency, R is
OUT
CC CC
Withthisbootstrapdiodeinstalled,thegatedrivercurrents
are generated directly by the buck-boost converter at high
efficiency rather than through the internal linear regulator.
To minimize current drawn from the output, the internal
the load resistance, and t
is the switch pin minimum
LOW
lowtime.Curvesshowingtheswitchpinminimumlowtime
can be found in the Typical Performance Characteristics
section of this data sheet. The parameter R represents
S
V
regulator contains reverse blocking circuitry which
the average series resistance of the power stage and can
be approximated as twice the average power switch re-
sistance plus the DC resistance of the inductor.
CC
minimizes the current into the PV /V pins when they
CC CC
are driven above the input voltage.
GBUCK = GDIVIDERGPWMGPOWER
PV
V
OUT
OUT
19.8
LTC3115-1
CC
GDIVIDER =
V
IN
V
PV
CC
GPWM = 1.5 1– t
f
(
)
LOW
4.7µF
31151 F06
V R
IN
GPOWER
=
1– t
f R+ R
)(
Figure 6. Bootstrapping PVCC and VCC
(
)
LOW
S
Notice that the gain of the analog divider cancels the input
voltage dependence of the power stage. As a result, the
buck mode gain is well approximated by a constant as
given by the following equation:
Buck Mode Small-Signal Model
The LTC3115-1 uses a voltage mode control loop to
maintain regulation of the output voltage. An externally
compensated error amplifier drives the VC pin to generate
the appropriate duty cycle of the power switches. Use of
an external compensation network provides the flexibility
for optimization of closed loop performance over the wide
variety of output voltages, switching frequencies, and ex-
ternal component values supported by the LTC3115-1.
R
R+ RS
GBUCK = 29.7
≅ 29.7= 29.5dB
The buck mode transfer function has a single zero which
is generated by the ESR of the output capacitor. The zero
frequency, f , is given by the following expression where
Z
The small-signal transfer function of the buck-boost
converter is different in the buck and boost modes of op-
eration and care must be taken to ensure stability in both
operating regions. When stepping down from a higher
input voltage to a lower output voltage, the converter
will operate in buck mode and the small-signal transfer
R and C are the ESR and value of the output filter ca-
C
O
pacitor respectively.
1
fZ =
2π RCCO
In most applications, an output capacitor with a very low
ESR is utilized in order to reduce the output voltage ripple
to acceptable levels. Such low values of capacitor ESR
result in a very high frequency zero and as a result the
zero is commonly too high in frequency to significantly
impact compensation of the feedback loop.
functionfromtheerroramplifieroutput,V ,totheconverter
output voltage is given by the following equation:
C
s
1+
2πf
VO
VC
Z
= GBUCK
2
s
s
BUCK MODE
1+
+
2πfOQ
2πf
O
31151f
21
LTC3115-1
APPLICATIONS INFORMATION
The denominator of the buck mode transfer function ex-
hibits a pair of resonant poles generated by the LC filtering
of the power stage. The resonant frequency of the power
The boost mode gain, G
, is comprised of three
BOOST
components:theanalogdivider,thepulsewidthmodulator
and the power stage. The gain of the analog divider and
PWM remain the same as in buck mode operation, but
the gain of the power stage in boost mode is given by the
following equation:
stage, f , is given by the following expression where L is
O
the value of the inductor:
R+ RS
1
1
1
fO =
≅
2
VOUT
2π LC R+ R
2π LCO
(
)
GPOWER
≅
O
C
1– t
f V
(
)
LOW
IN
Thequalityfactor,Q,hasasignificantimpactoncompensa-
tion of the voltage loop since a higher Q factor produces
a sharper loss of phase near the resonant frequency. The
qualityfactorisinverselyrelatedtotheamountofdamping
in the power stage and is substantially influenced by the
By combining the individual terms, the total gain in boost
mode can be reduced to the following expression. Notice
that unlike in buck mode, the gain in boost mode is a
function of both the input and output voltage.
average series resistance of the power stage, R . Lower
2
S
29.7VOUT
GBOOST
≅
values of R will increase the Q and result in a sharper
S
2
V
IN
loss of phase near the resonant frequency and will require
more phase boost or lower bandwidth to maintain an
adequate phase margin.
In boost mode operation, the frequency of the right half
plane zero, f , is given by the following expression.
The frequency of the right half plane zero decreases at
higher loads and with larger inductors.
RHPZ
LC R+ R R+ R
(
C )(
)
C
LCO
O
S
Q =
≅
L
R
RR C + L+ C R R+ R
(
)
C O
O
S
+ CORS
2
2
R 1– t
f V
(
)
LOW
IN
fRHPZ
=
2
2π LVOUT
Boost Mode Small-Signal Model
In boost mode, the resonant frequency of the power stage
hasadependenceontheinputandoutputvoltageasshown
by the following equation.
When stepping up from a lower input voltage to a higher
output voltage, the buck-boost converter will operate in
boost mode where the small-signal transfer function from
control voltage, V , to the output voltage is given by the
C
2
RV
IN
RS +
following expression.
2
VOUT
V
1
1
1
IN
fO =
≅
•
s
2π f
s
2π LC R+ R
2π VOUT LC
(
)
O
C
1+
1–
2π f
VO
VC
Z
RHPZ
= GBOOST
Finally, the magnitude of the quality factor of the power
stage in boost mode operation is given by the following
expression.
2
s
s
BOOST MODE
1+
+
2π fOQ
2π f
O
2
Inboostmodeoperation,thetransferfunctionischaracter-
ized by a pair of resonant poles and a zero generated by
the ESR of the output capacitor as in buck mode. However,
in addition there is a right half plane zero which generates
increasing gain and decreasing phase at higher frequen-
cies. As a result, the crossover frequency in boost mode
operation generally must be set lower than in buck mode
in order to maintain sufficient phase margin.
RVIN
VOUT
LCOR RS +
2
Q =
L+ CORSR
31151f
22
LTC3115-1
APPLICATIONS INFORMATION
Compensation of the Voltage Loop
V
OUT
LTC3115-1
1000mV
FB
+
–
R
The small-signal models of the LTC3115-1 reveal that the
transfer function from the error amplifier output, VC, to
the output voltage is characterized by a set of resonant
poles and a possible zero generated by the ESR of the
output capacitor as shown in the Bode plot of Figure 7.
In boost mode operation, there is an additional right half
plane zero that produces phase lag and increasing gain at
higher frequencies. Typically, the compensation network
is designed to ensure that the loop crossover frequency
is low enough that the phase loss from the right half
plane zero is minimized. The low frequency gain in buck
TOP
C1
R
BOT
VC
GND
31151 F08
Figure 8. Error Amplifier with Type I Compensation
Inmostapplications, thelowbandwidthoftheTypeIcom-
pensatedloopwillnotprovidesufficienttransientresponse
performance. To obtain a wider bandwidth feedback loop,
optimize the transient response, and minimize the size of
the output capacitor, a Type III compensation network as
shown in Figure 9 is required.
mode is a constant, but varies with both V and V
in
IN
OUT
boost mode.
GAIN
V
OUT
R
FF
LTC3115-1
–40dB/DEC
1000mV
FB
+
–
R
R
C
FF
TOP
C
FB
R
BOT
FB
–20dB/DEC
VC
GND
C
POLE
PHASE
31151 F09
0°
–90°
BUCK MODE
–180°
–270°
Figure 9. Error Amplifier with Type III Compensation
BOOST MODE
f
31151 F07
A Bode plot of the typical Type III compensation network
is shown in Figure 10. The Type III compensation network
provides a pole near the origin which produces a very high
loop gain at DC to minimize any steady-state error in the
f
f
O
RHPZ
Figure 7. Buck-Boost Converter Bode Plot
regulation voltage. Two zeros located at f
and f
ZERO1
ZERO2
For charging or other applications that do not require an
optimizedoutputvoltagetransientresponse,asimpleType
I compensation network as shown in Figure 8 can be used
to stabilize the voltage loop. To ensure sufficient phase
margin, the gain of the error amplifier must be low enough
that the resultant crossover frequency of the control loop
is well below the resonant frequency.
provide sufficient phase boost to allow the loop crossover
frequency to be set above the resonant frequency, f , of
O
the power stage. The Type III compensation network also
introduces a second and third pole. The second pole, at
frequency f
, reduces the error amplifier gain to a
POLE2
zero slope to prevent the loop crossover from extending
too high in frequency. The third pole at frequency f
provides attenuation of high frequency switching noise.
POLE3
31151f
23
LTC3115-1
APPLICATIONS INFORMATION
Inmostapplicationsthecompensationnetworkisdesigned
sothattheloopcrossoverfrequencyisabovetheresonant
frequency of the power stage, but sufficiently below the
boostmoderighthalfplanezerotominimizetheadditional
phaseloss.Oncethecrossoverfrequencyisdecidedupon,
the phase boost provided by the compensation network
is centered at that point in order to maximize the phase
margin. A larger separation in frequency between the
zeros and higher order poles will provide a higher peak
phase boost but may also increase the gain of the error
amplifier which can push out the loop crossover to a
higher frequency.
GAIN
–20dB/DEC
–20dB/DEC
90°
0°
PHASE
–90°
f
f
f
f
ZERO1
POLE2 POLE3
31151 F10
f
ZERO2
Figure 10. Type III Compensation Bode Plot
The Q of the power stage can have a significant influence
on the design of the compensation network because it
determineshowrapidlythe180°ofphaselossinthepower
The transfer function of the compensated Type III error
amplifierfromtheinputoftheresistordividertotheoutput
of the error amplifier, VC, is:
stage occurs. For very low values of series resistance, R ,
S
the Q will be higher and the phase loss will occur sharply.
In such cases, the phase of the power stage will fall rapidly
to–180°abovetheresonantfrequencyandthetotalphase
margin must be provided by the compensation network.
s
s
1+
1+
2π f
2π f
VC(s)
OUT(s)
ZERO1
ZERO2
= GEA
V
POLE1
s
s
However, with higher losses in the power stage (larger R )
s 1+
1+
S
2π f
2π f
POLE2
the Q factor will be lower and the phase loss will occur
more gradually. As a result, the power stage phase will not
be as close to –180° at the crossover frequency and less
phase boost is required of the compensation network.
The error amplifier gain is given by the following equation.
The simpler approximate value is sufficiently accurate in
most cases since C is typically much larger in value
FB
The LTC3115-1 error amplifier is designed to have a
fixed maximum bandwidth in order to provide rejection
of switching noise to prevent it from interfering with the
control loop. From a frequency domain perspective, this
can be viewed as an additional single pole as illustrated in
Figure 11. The nominal frequency of this pole is 300kHz.
For typical loop crossover frequencies below about 50kHz
the phase contributed by this additional pole is negligible.
However, for loops with higher crossover frequencies this
additional phase loss should be taken into account when
designing the compensation network.
than C
.
POLE
1
1
GEA =
≅
RTOP C + C
RTOPCFB
(
)
FB
POLE
ThepoleandzerofrequenciesoftheTypeIIIcompensation
network can be calculated from the following equations
where all frequencies are in Hz, resistances are in ohms,
and capacitances are in farads.
1
fZERO1
fZERO2
fPOLE2
fPOLE3
=
=
=
=
2π RFBCFB
1
+ RFF
1
≅
LTC3115-1
R
2π R
C
2π RTOPCFF
(
)
TOP
FF
FILT
1000mV
FB
+
–
INTERNAL
VC
CFB + CPOLE
2πCFBCPOLERFB 2π CPOLERFB
1
C
FILT
VC
≅
31151 F11
1
Figure 11. Internal Loop Filter
2πCFFRFF
31151f
24
LTC3115-1
APPLICATIONS INFORMATION
Loop Compensation Example
pensated loop. A reasonable starting point is to assume
that the compensation network will generate a peak phase
boost of approximately 60°. Therefore, in order to obtain
This section provides an example illustrating the design of
a compensation network for a typical LTC3115-1 applica-
tion circuit. In this example a 5V regulated output voltage
is generated with the ability to supply a 500mA load from
aninputpowersourcerangingfrom3.5Vto30V. Toreduce
switching losses a 750kHz switching frequency has been
chosen for this example. In this application the maximum
inductor current ripple will occur at the highest input volt-
age. An inductor value of 8.2µH has been chosen to limit
the worst-case inductor current ripple to approximately
600mA. A low ESR output capacitor with a value of 20µF
is specified to yield a worst-case output voltage ripple
(occurring at the worst-case step-up ratio and maximum
load current) of approximately 12mV. In summary, the key
power stage specifications for this LTC3115-1 example
application are given below.
a phase margin of 60°, the loop crossover frequency, f ,
C
should be selected as the frequency at which the phase
of the buck-boost converter reaches –180°. As a result,
at the loop crossover frequency the total phase will be
simply the 60° of phase provided by the error amplifier
as shown:
Phase Margin = φ
+ φ
+180°
BUCK-BOOST
ERRORAMPLIFIER
= –180° + 60° + 180° = 60°
Similarly, if a phase margin of 45° is required, the target
crossover frequency should be picked as the frequency
at which the buck-boost converter phase reaches –195°
so that the combined phase at the crossover frequency
yields the desired 45° of phase margin.
This example will be designed for a 60° phase margin to
ensure adequate performance over parametric variations
and varying operating conditions. As a result, the target
f = 0.75MHz, t
= 0.1µs
LOW
V = 3.5V to 30V
IN
V
OUT
C
OUT
= 5V at 500mA
crossover frequency, f , will be the point at which the
C
phase of the buck-boost converter reaches –180°. It is
generally difficult to determine this frequency analytically
given that it is significantly impacted by the Q factor of
the resonance in the power stage. As a result, it is best
determined from a Bode plot of the buck-boost converter
as shown in Figure 12. This Bode plot is for the LTC3115-1
buck-boostconverterusingthepreviouslyspecifiedpower
stageparametersandwasgeneratedfromthesmall-signal
model equations using LTspice® software. In this case, the
= 20µF, R = 10mΩ
C
L = 8.2µH, R = 45mΩ
L
Withthepowerstageparametersspecified,thecompensa-
tion network can be designed. In most applications, the
most challenging compensation corner is boost mode
operation at the greatest step-up ratio and highest load
currentsincethisgeneratesthelowestfrequencyrighthalf
planezeroandresultsinthegreatestphaseloss.Therefore,
a reasonable approach is to design the compensation
network at this worst-case corner and then verify that
sufficient phase margin exists across all other operating
phasereaches–180°at24kHzmakingf =24kHzthetarget
C
crossover frequency for the compensated loop.
From the Bode plot of Figure 12 the gain of the power
stageatthetargetcrossoverfrequencyis19dB.Therefore,
in order to make this frequency the crossover frequency
conditions. In this example application, at V = 3.5V and
IN
the full 500mA load current, the right half plane zero will
be located at 70kHz and this will be a dominant factor in
determining the bandwidth of the control loop.
in the compensated loop, the total loop gain at f must
C
be adjusted to 0dB. To achieve this, the gain of the com-
pensation network must be designed to be –19dB at the
crossover frequency.
The first step in designing the compensation network is
to determine the target crossover frequency for the com-
31151f
25
LTC3115-1
APPLICATIONS INFORMATION
the compensated error amplifier is determined simply by
the amount of separation between the poles and zeros as
shown by the following equation:
50
40
30
20
0
–40
–80
–120
GAIN
PHASE
f
f
–1
P
Z
φ
= 4 tan
– 270°
MAX
10
0
–160
–200
A reasonable choice is to pick the frequency of the poles,
f , to be about 50 times higher than the frequency of the
–10
–20
–30
–240
–280
–320
P
zeros, f , which provides a peak phase boost of approxi-
Z
f
C
mately φ
= 60° as was assumed previously. Next, the
MAX
100
1k
FREQUENCY (Hz)
100k
10
1M
10k
phase boost must be centered so that the peak phase
occurs at the target crossover frequency. The frequency
31151 F12
of the maximum phase boost, f
, is the geometric
CENTER
Figure 12. Converter Bode Plot, VIN = 3.5V, ILOAD = 500mA
mean of the pole and zero frequencies as:
fCENTER = fP • fZ = 50• fZ ≅ 7• fZ
At this point in the design process, there are three con-
straints that have been established for the compensation
Therefore, inordertocenterthephaseboostgivenafactor
of 50 separation between the pole and zero frequencies,
the zeros should be located at one seventh of the cross-
over frequency and the poles should be located at seven
times the crossover frequency as given by the following
equations:
network. It must have –19dB gain at f = 24kHz, a peak
C
phase boost of 60° and the phase boost must be centered
at f = 24kHz. One way to design a compensation network
C
tomeetthesetargetsistosimulatethecompensatederror
amplifierBodeplotinLTspiceforthetypicalcompensation
network shown on the front page of this data sheet. Then,
the gain, pole frequencies and zero frequencies can be
iteratively adjusted until the required constraints are met.
1
7
1
7
fZ = • fC = 24kHz = 3.43kHz
(
)
Alternatively, an analytical approach can beusedto design
a compensation network with the desired phase boost,
center frequency and gain. In general, this procedure can
be cumbersome due to the large number of degrees of
freedom in a Type III compensation network. However the
design process can be simplified by assuming that both
f = 7• f = 7 24kHz = 168kHz
(
)
P
C
Thisplacementofthepolesandzeroswillyieldapeakphase
boost of 60° that is centered at the crossover frequency,
f . Next, in order to produce the desired target crossover
C
frequency, the gain of the compensation network at the
point of maximum phase boost, G
, must be set to
compensation zeros occur at the same frequency, f , and
CENTER
Z
–19dB. The gain of the compensated error amplifier at the
both higher order poles (f
and f
) occur at the
POLE2
POLE3
point of maximum phase gain is given by:
common frequency, f . In most cases this is a reasonable
P
assumption since the zeros are typically located between
1kHz and 10kHz and the poles are typically located near
each other at much higher frequencies. Given this as-
2π fP
GCENTER = 10log
dB
3
2
2π f
RTOPCFB
(
(
)
)
Z
sumption, the maximum phase boost, f
, provided by
MAX
31151f
26
LTC3115-1
APPLICATIONS INFORMATION
Assuming a multiple of 50 separation between the pole
frequencies and zero frequencies this can be simplified
to the following expression:
Next, C can be chosen to set the second zero, f
, to
FF
ZERO2
the common zero frequency of 3.43kHz.
1
CFF =
≅ 47pF
2π 1MΩ 3.43kHz
)(
50
(
)
GCENTER = 20log
dB
2π fCRTOPCFB
Finally, the resistor value R can be chosen to place the
FF
second pole at 168kHz.
This equation completes the set of constraints needed to
determine the compensation component values. Specifi-
1
RFF =
≅ 20.0kΩ
cally, the two zeros, f
and f
, should be located
ZERO1
ZERO2
2π 47pF 168Hz
)(
(
)
near 3.43kHz. The two poles, f
and f
, should be
POLE2
POLE3
located near 168kHz and the gain should be set to provide
a gain at the crossover frequency of G = –19dB.
Now that the pole frequencies, zero frequencies and gain
of the compensation network have been established, the
next step is to generate a Bode plot for the compensated
error amplifier to confirm its gain and phase properties.
A Bode plot of the error amplifier with the designed com-
pensation component values is shown in Figure 13. The
Bode plot confirms that the peak phase occurs at 24kHz
and the phase boost at that point is 57.7°. In addition,
the gain at the peak phase frequency is –19.3dB which is
close to the design target.
CENTER
The first step in defining the compensation component
valuesistopickavalueforR thatprovidesanacceptably
TOP
low quiescent current through the resistor divider. A value
of R
FB
= 1MΩ is a reasonable choice. Next, the value of
TOP
C
can be found in order to set the error amplifier gain
at the crossover frequency to –19dB as follows:
G
= –19.1dB
CENTER
50
= 20log
15
10
90
60
2π 24kHz 1MΩ C
(
) (
)
FB
50
5
C
=
≅ 3.0nF
PHASE
FB
0
–19.1
20
2π 24kHz 1MΩ alog
) (
30
(
)
–5
GAIN
–10
–15
–20
–25
–30
–35
–40
0
The compensation poles can be set at 168kHz and the
zeros at 3.43kHz by using the expressions for the pole
andzerofrequenciesgivenintheprevioussection. Setting
–30
–60
–90
the frequency of the first zero, f
, to 3.43kHz results
ZERO1
f
C
in the following value for R :
FB
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
1
3115 F13
RFB =
≅ 15.4kΩ
2π 3nF 3.43kHz
(
)(
)
Figure 13. Compensated Error Amplifier Bode Plot
This leaves the free parameter, C
POLE1
given:
, to set the frequency
POLE
f
to the common pole frequency of 168kHz as
1
CPOLE
=
≅ 62pF
2π 15.4kΩ 168kHz
(
)(
)
31151f
27
LTC3115-1
APPLICATIONS INFORMATION
ThefinalstepinthedesignprocessistocomputetheBode
plot for the entire loop using the designed compensation
network and confirm its phase margin and crossover
frequency. The complete loop Bode plot for this example
is shown in Figure 14. The loop crossover frequency is
22kHz which is close to the design target and the phase
margin is approximately 60°.
In addition to setting the output voltage, the value of
is instrumental in controlling the dynamics of the
compensation network. When changing the value of this
resistor, care must be taken to understand the impact this
will have on the compensation network.
R
TOP
In addition, the Thevenin equivalent resistance of the
resistor divider controls the gain of the current limit. To
maintain sufficient gain in this loop, it is recommended
TheBodeplotforthecompleteloopshouldbecheckedover
all operating conditions and for variations in component
values to ensure that sufficient phase margin exists in all
cases. The stability of the loop should also be confirmed
viatimedomainsimulationandbyevaluatingthetransient
response of the converter in the actual circuit.
that the value of R
be chosen to be 1MΩ or larger.
TOP
Switching Frequency Selection
The switching frequency is set by the value of a resistor
connected between the RT pin and ground. The switching
frequency,f,isrelatedtotheresistorvaluebythefollowing
Output Voltage Programming
equation where R is the resistance:
T
The output voltage is set via the external resistor divider
35.7MHz
f =
comprisedofresistorsR andR asshowinFigures 8
TOP
BOT
R /kΩ
(
)
T
and 9. The resistor divider values determine the output
regulation voltage according to:
Higher switching frequencies facilitate the use of smaller
inductors as well as smaller input and output filter capaci-
tors which results in a smaller solution size and reduced
componentheight.However,higherswitchingfrequencies
also generally reduce conversion efficiency due to the
increased switching losses.
RTOP
RBOT
VOUT = 1.000V 1+
60
180
120
PHASE
40
In addition, higher switching frequencies (above 750kHz)
will reduce the maximum output current that can be sup-
plied(seeTypicalPerformanceCharacteristicsfordetails).
20
0
60
0
GAIN
For applications with V
≥ 20V, a maximum switching
OUT
frequency of 1MHz is recommended.
–20
–40
–60
–60
–120
f
C
–180
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
31151 F14
Figure 14. Complete Loop Bode Plot
31151f
28
LTC3115-1
APPLICATIONS INFORMATION
PCB Layout Considerations
4. Connections to all of the components shown in bold
shouldbemadeaswideaspossibletoreducetheseries
resistance.Thiswillimproveefficiencyandmaximizethe
output current capability of the buck-boost converter.
The LTC3115-1 buck-boost converter switches large
currents at high frequencies. Special attention should be
paid to the PC board layout to ensure a stable, noise-free
and efficient application circuit. Figures 15 and 16 show
a representative PCB layout for each package option to
outline some of the primary considerations. A few key
guidelines are provided below:
5. To prevent large circulating currents in the ground
plane from disrupting operation of the LTC3115-1, all
small-signal grounds should return directly to GND
by way of a dedicated Kelvin route. This includes the
ground connection for the RT pin resistor, and the
ground connection for the feedback network as shown
in Figures 15 and 16.
1. The parasitic inductance and resistance of all circulat-
ing high current paths should be minimized. This can
be accomplished by keeping the routes to all bold
components in Figures 15 and 16 as short and as wide
as possible. Capacitor ground connections should via
down to the ground plane by way of the shortest route
6. Keep the routes connecting to the high impedance,
noise sensitive inputs FB and RT as short as possible
to reduce noise pick-up.
possible. The bypass capacitors on PV , PV
and
IN
OUT
7. The BST1 and BST2 pins transition at the switching
frequency to the full input and output voltage respec-
tively. To minimize radiated noise and coupling, keep
the BST1 and BST2 routes as short as possible and
away from all sensitive circuitry and pins (VC, FB, RT).
In many applications the length of traces connecting to
the boost capacitors can be minimized by placing the
boost capacitors on the back side of the PC board and
routing to them via traces on an internal copper layer.
PV /V should be placed as close to the IC as pos-
CC CC
sible and should have the shortest possible paths to
ground.
2. Theexposedpadistheelectricalpowergroundconnec-
tionfortheLTC3115-1intheDHDpackage.Multiplevias
shouldconnectthebackpaddirectlytothegroundplane.
Inaddition,maximizationofthemetallizationconnected
to the backpad will improve the thermal environment
and improve the power handling capabilities of the IC
in both the FE and DHD packages.
3. The components shown in bold and their connections
should all be placed over a complete ground plane to
minimize loop cross-sectional areas. This minimizes
EMI and reduces inductive drops.
31151f
29
LTC3115-1
APPLICATIONS INFORMATION
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
[16]
PWM/
SYNC
[1]
RUN
[2]
SW2
[15]
SW1
[17]
PGND
V
OUT
V
IN
[3]
PV
[14]
IN
PV
OUT
C
C
BST1
[4]
[13]
GND
BST1
INNER PCB
LAYER ROUTES
KELVIN
BACK TO
GND PIN
BST2
[5]
GND
[12]
BST2
[6]
VC
[11]
CC
PV
R
R
BOT
[7]
FB
[10]
R
T
V
IN
TOP
[8]
RT
[9]
CC
V
KELVIN
TO V
31151 F15
OUT
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
Figure 15. PCB Layout Recommended for the DHD Package
31151f
30
LTC3115-1
APPLICATIONS INFORMATION
VIA TO GROUND PLANE
(AND TO INNER LAYER
WHERE SHOWN)
[1]
PGND
[20]
PGND
[19]
PWM/
SYNC
[2]
RUN
[3]
SW2
[18]
SW1
[21]
PGND
V
OUT
V
IN
[4]
OUT
[17]
IN
PV
PV
C
C
BST1
BST2
[5]
[16]
GND
BST1
INNER PCB
LAYER ROUTES
KELVIN
BACK TO
GND PIN
[6]
GND
[15]
BST2
[7]
VC
[14]
CC
PV
R
BOT
[8]
FB
[13]
IN
R
T
V
R
TOP
[9]
RT
[12]
CC
V
KELVIN
TO V
31151 F16
OUT
[10]
PGND
[11]
PGND
UNINTERRUPTED GROUND PLANE SHOULD EXIST UNDER ALL COMPONENTS SHOWN IN
BOLD AND UNDER TRACES CONNECTING TO THOSE COMPONENTS
Figure 16. PCB Layout Recommended for the FE Package
31151f
31
LTC3115-1
TYPICAL APPLICATIONS
Wide Input Voltage Range (2.7V to 40V), High Efficiency 300kHz, Low Noise 5V Regulator
L1
33µH
C
C
BST2
0.1µF
BST1
0.1µF
BST1 SW1
PV
SW2 BST2
PV
5V
2.7V TO
40V
1A V > 3.6V
IN
IN
OUT
+
C
2A V ≥ 6V
IN
IN
C
V
O
IN
C
R
10µF
FF
TOP
330µF
RUN
82pF
1M
C
FB
R
93.1k
FB
LTC3115-1
3300pF
R
FF
249k
VC
27pF
FB
R
BOT
249k
D1
PWM/SYNC
31151 TA02a
PV
CC
V
CC
RT
C1
4.7µF
R
T
GND
PGND
121k
C
: MURATA GRM55DR61H106K
IN
O
C : POSCAP 6TPB330M (7.3mm × 4.3mm × 2.8mm)
D1: PANASONIC MA785
L1: COILCRAFT MSS1260
PWM Mode Efficiency
vs Load Current
PWM Mode Efficiency
vs Load Current
100
95
100
95
90
90
85
85
80
75
80
75
70
65
60
55
50
70
65
60
55
50
V
V
V
= 5V
= 3.6V
= 2.7V
V
V
V
= 12V
= 24V
= 36V
IN
IN
IN
IN
IN
IN
0.01
0.1
1
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
31151 TA02b
31151 TA02c
VOUT Transient for a 0A to 1A Load Step
VOUT Transient for a 0A to 2A Load Step, VIN = 24V
V
= 36V
= 12V
= 5V
V
IN
OUT
(200mV/DIV)
V
OUT
(200mV/DIV)
V
IN
V
OUT
(200mV/DIV)
INDUCTOR CURRENT
(2A/DIV)
V
IN
V
OUT
(200mV/DIV)
LOAD CURRENT
(2A/DIV)
V
= 3.6V
IN
V
OUT
(200mV/DIV)
31151 TA02d
31151 TA02e
2ms/DIV
2ms/DIV
31151f
32
LTC3115-1
TYPICAL APPLICATIONS
Wide Input Voltage Range (10V to 40V) 1MHz 24V Supply at 500mA
L1
15µH
C
C
BST2
0.1µF
BST1
0.1µF
BST1 SW1
PV
SW2 BST2
24V
500mA
10V TO 40V
PV
OUT
IN
C
C
O
IN
V
IN
C
FF
R
10µF
10µF
TOP
R1
22pF
UVLO
1M
953k
C
FB
PROGRAMMED
TO 10V (1.3V
HYSTERESIS)
R
FB
3300pF
RUN
LTC3115-1
R
FF
10k
10k
R2
130k
VC
FB
R
BOT
PWM/SYNC
43.2k
PV
CC
V
CC
RT
C1
R
T
GND
PGND
4.7µF
35.7k
31151 TA03a
L1: WÜRTH 744 066 150
Maximum Load Current vs VIN
Efficiency vs VIN
92
2.5
2.0
1.5
1.0
0.5
0
I
= 0.5A
LOAD
90
88
86
84
82
80
I
= 1A
LOAD
10
20
30
40
10
20
30
INPUT VOLTAGE (V)
40
INPUT VOLTAGE (V)
31151 TA03c
31151 TA03b
Power-Up/Down Waveforms,
ILOAD = 0.5A
V
IN
(5V/DIV)
V
OUT
(10V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
31151 TA03d
50ms/DIV
31151f
33
LTC3115-1
TYPICAL APPLICATIONS
Industrial 12V 1MHz Regulator with Custom Input Undervoltage Lockout Thresholds
L1
10µH
C
C
BST2
0.1µF
BST1
0.1µF
BST1 SW1
PV
SW2 BST2
12V
1.4A
10V TO
40V
PV
OUT
IN
C
C
O
IN
V
IN
C
FF
R
10µF
22µF
TOP
33pF
1M
C
FB
R
FB
820pF
ENABLED WHEN V
R1
IN
R
FF
10k
LTC3115-1
40.2k
REACHES 10.6V
2M
VC
FB
RUN
RT
DISABLED WHEN V
FALLS BELOW 8.7V
R2
255k
IN
R
90.9k
PWM/SYNC
BOT
PV
CC
V
CC
C1
4.7µF
31151 TA04a
R
35.7k
T
GND
PGND
C
: MURATA GRM55DR61H106K
IN
C : TDK CKG57NX5R1H226M
O
L1: WÜRTH 744065100
PWM Mode Efficiency
vs Load Current
0A to 1.5A Load Step, VIN = 24V
100
90
80
70
60
50
40
V
OUT
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
V
= 10.6V
31151 TA04c
IN
500µs/DIV
V
V
V
= 12V
= 24V
= 36V
IN
IN
IN
0.01
0.1
1
LOAD CURRENT (A)
31151 TA04b
0A to 1.5A Load Step, VIN = 10.6V
0A to 1.5A Load Step, VIN = 40V
V
V
OUT
OUT
(500mV/DIV)
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 TA04d
31151 TA04e
500µs/DIV
500µs/DIV
31151f
34
LTC3115-1
TYPICAL APPLICATIONS
24V 750kHz Industrial Rail Restorer
L1
22µH
*
*OPTIONAL: INSTALL IN
APPLICATIONS SUBJECT TO
OUTPUT OVERLOAD OR
C
C
BST2
0.1µF
BST1
0.1µF
SHORT-CIRCUIT CONDITIONS
BST1 SW1
PV
SW2 BST2
PV
24V
1.5A
20V TO 40V
IN
OUT
+
C
IN
R1
500k
C
V
1µF
O
IN
C
R
10µF
FF
OPEN
DRAIN
OUTPUT
TOP
82µF
47pF
1M
C
FB
RUN
R
LTC3115-1
FB
3300pF
R
FF
51k
25k
ON OFF
VC
100pF
FB
RT
R
BOT
43.2k
R
T
PWM/SYNC
47.5k
PV
CC
V
CC
C1
GND
PGND
4.7µF
31151 TA05a
C : OS-CON 35SVPF82M
O
L1: TOKO 892NBS-220M
Regulated Output Voltage from a
Time Varying Input Rail
0A to 1.5A Load Step, VIN = 20V
LOAD
CURRENT
(1A/DIV)
40V
V
IN
(5V/DIV)
V
OUT
(1V/DIV)
V
OUT
(5V/DIV)
INDUCTOR
CURRENT
(2A/DIV)
20V
31151 TA05b
31151 TA05c
10ms/DIV
500µs/DIV
Efficiency vs Load Current
100
90
80
70
60
50
40
30
V
V
V
= 20V
= 24V
= 36V
IN
IN
IN
20
0.01
0.10
1
LOAD CURRENT (A)
31151 TA05d
31151f
35
LTC3115-1
TYPICAL APPLICATIONS
USB, FireWire, Automotive and Unregulated Wall Adapter to Regulated 5V (750kHz)
D1
D2
D3
D4
USB
4.1V TO 5.5V
L1
FireWire
8V TO 36V
10µH
C
C
BST2
BST1
AUTOMOTIVE
3.6V TO 40V
0.1µF
0.1µF
BST1 SW1
PV
V
SW2 BST2
5V
WALL ADAPTER
4V TO 40V
PV
IN
OUT
750mA
C
O
10µF
IN
C
47µF
R
FF
TOP
47pF
×2
LTC3115-1
1M
C
FB
R
FB
4700pF
PWM/SYNC
RUN
BURST PWM
OFF ON
R
FF
100k
51k
VC
FB
R
BOT
249k
PV
V
CC
CC
RT
C1
4.7µF
31151 TA06a
R
T
GND
PGND
47.5k
C
: MURATA GRM55DR61H106K
IN
C : GRM43ER60J476
O
D1-D4: B360A-13-F
L1: COILCRAFT LPS6225
Soft-Start Waveform, VIN = 24V, ILOAD = 0.5A
V
RUN
(5V/DIV)
V
CC
(5V/DIV)
Efficiency vs Load Current,
from Automotive Input
V
OUT
(2V/DIV)
100
90
80
70
60
50
40
30
20
INDUCTOR
CURRENT
(500mA/DIV)
31151 TA06c
2ms/DIV
Output Voltage Transient Response,
750mA Load Step, Powered from Automotive Input
V
V
V
V
V
= 3.6V
IN
IN
IN
IN
IN
= 5V
= 12V
= 24V
= 36V
V
V
= 36V
= 12V
= 3.6V
IN
IN
IN
V
OUT
(200mV/DIV)
V
OUT
0.01
0.1
1
(200mV/DIV)
LOAD CURRENT (A)
V
V
OUT
31151 TA06b
(200mV/DIV)
31151 TA06d
1ms/DIV
31151f
36
LTC3115-1
TYPICAL APPLICATIONS
Miniature Size 1.5MHz 12V Supply
L1
4.7µH
C
C
BST2
0.1µF
BST1
0.1µF
BST1 SW1
PV
SW2 BST2
12V AT 500mA
1A V > 10V
6V TO 40V
PV
OUT
IN
IN
C
C
O
I
V
IN
R
C
FF
4.7µF
10µF
TOP
RUN
1M
33pF
C
FB
R
15k
LTC3115-1
FB
1000pF
R
FF
15k
BURST PWM
PWM/SYNC
RT
VC
FB
R
23.7k
T
R
90.9k
BOT
PV
V
CC
CC
31151 TA07a
C1
4.7µF
GND
PGND
C : MURATA GRM55DR61H106K
O
L1: WÜRTH 7447789004
Load Step Transient Response, 0mA to 500mA,
IN = 6V
Load Step Transient Response, 0mA to 500mA,
VIN = 24V
V
LOAD CURRENT
(500mA/DIV)
LOAD CURRENT
(500mA/DIV)
V
V
OUT
OUT
(500mV/DIV)
(500mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 TA07b
31151 TA07c
200µs/DIV
200µs/DIV
Efficiency vs Load Current, PWM Mode
Efficiency vs Load Current, Burst Mode Operation
100
90
80
70
60
50
40
90
80
70
60
50
40
30
20
V
V
V
V
= 6V
V
V
V
V
= 6V
IN
IN
IN
IN
IN
IN
IN
IN
= 10V
= 24V
= 36V
= 10V
= 24V
= 36V
30
20
0.1
0.01
0.1
1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (mA)
31151 TA07d
31151 TA07e
31151f
37
LTC3115-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.44 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 ± 0.10
5.00 ±0.10
(2 SIDES)
9
16
R = 0.20
TYP
4.00 ±0.10 2.44 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHD16) DFN 0504
8
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
4.34 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
31151f
38
LTC3115-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CA
6.40 – 6.60*
4.95
(.195)
(.252 – .260)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74
SEE NOTE 4
(.252)
(.108)
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CA) TSSOP REV I 0211
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
31151f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC3115-1
TYPICAL APPLICATION
750kHz Automotive 5V Regulator with Cold Crank Capability
L1
6.8µH
C
BST1
0.1µF
C
BST2
0.1µF
BST1 SW1
PV
SW2 BST2
AUTOMOTIVE
3.6V TO 40V
5V
1A
PV
OUT
IN
C
C
O
IN
10µF
V
IN
C
R
47µF
FF
TOP
33pF
LTC3115-1
1M
C
FB
R
FB
1000pF
R
PWM/SYNC
RUN
FF
BURST PWM
OFF ON
54.9k
42.2k
D1*
VC
FB
R
249k
C
: MURATA GRM55DR61H106K
BOT
IN
C : MURATA GRM43ER60J476K
O
D1: PANASONIC MA785
L1: SUMIDA CDRH8D43HPNP
PV
V
CC
CC
RT
C1
4.7µF
31151 TA08a
R
47.5k
T
GND
PGND
*OPTIONAL-INSTALL D1 FOR IMPROVED EFFICIENCY AND LOWER INPUT OPERATING VOLTAGE
Efficiency vs Load Current
IN = 12V
Cold Crank Line Transient with 1A Load
Load Dump Line Transient with 1A Load
V
100
90
80
70
60
50
40
30
20
40V
12V
V
IN
V
(10V/DIV)
IN
15ms FALL TIME
4.5V
(2V/DIV)
13.8V
6V
V
OUT
(200mV/DIV)
V
OUT
(200mV/DIV)
INDUCTOR
CURRENT
(1A/DIV)
INDUCTOR
CURRENT
(1A/DIV)
31151 TA08b
31151 TA08c
200ms/DIV
2ms/DIV
WITH BOOTSTRAP DIODE
WITHOUT BOOTSTRAP DIODE
0.01
0.1
1
LOAD CURRENT (A)
31151 TA08d
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3112
LTC3113
LTC3127
LTC3789
LTC3785
LTC3534
2.5A (I ), 15V Synchronous Buck-Boost DC/DC Converter
V : 2.7V to 15V, V : 2.5V to 14V, I = 40µA, I < 1µA, DFN and
OUT
IN
OUT
Q
SD
TSSOP Packages
3A (I ), 2MHz Synchronous Buck-Boost DC/DC Converter
V : 1.8V to 5.5V, V : 1.8V to 5.25V, I = 30µA, ISD < 1µA, DFN
IN OUT Q
OUT
and TSSOP Packages
96% Efficiency V : 1.8V to 5.5V, V : 1.8V to 5.25V, I = 35µA,
1A (I ), 1.2MHz Buck-Boost DC/DC Converter with
OUT
IN
OUT
Q
Programmable Input Current Limit
I
< 4µA, MSOP and DFN Packages
SD
High Efficiency, Synchronous, 4-Switch Buck-Boost Controller
V : 4V to 38V, V : 0.8V to 38V, I = 3mA, I < 60µA,
IN OUT Q SD
SSOP-28, QFN-28 Packages
≤10A (I ), High Efficiency, 1MHz Synchronous, No R
™
V : 2.7V to 10V, V : 2.7V to 10V, I = 86µA, I < 15µA,
OUT
SENSE
IN
OUT
Q
SD
Buck-Boost Controller
QFN Package
7V, 500mA (I ), 1MHz Synchronous Buck-Boost DC/DC
94% Efficiency, V : 2.4V to 7V, V : 1.8V to 7V, I = 25µA,
OUT
IN
OUT
Q
Converter
I
< 1µA, DFN and GN Packages
SD
31151f
LT 0312 • PRINTED IN USA
40 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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